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1 pf1157-02 S1C88816 8-bit single chip microcomputer description the S1C88816 microcomputer features the s1c88 (model 3) cmos 8-bit core cpu along with a 116k bytes of rom, an 8k bytes of ram, three different timers, a serial interface with optional asynchronization or clock synchronization, a melody generator and an a/d converter. the S1C88816 has large capacity of rom and ram and fully operable over a wide range of voltages. furthermore, it can perform high speed operations even at low voltage. like all the equipment in the s1c family, these microcomputers have low power consumption. features core cpu ................................... s1c88 (model3) cmos 8-bit core cpu osc1 oscillation circuit ............. crystal oscillation circuit/cr oscillation circuit/external clock input 32.768 khz (typ.) osc3 oscillation circuit ............. crystal oscillation circuit/ceramic oscillation circuit/cr oscillation circuit/ external clock input 8.2 mhz (max.) instruction set ............................. 608 types (usable for multiplication and division instructions) min. instruction execution time .. 0.244 ?ec/8.2 mhz (2 clock) internal rom capacity ............... 116k bytes internal ram capacity ................ 8k bytes/ram, 4224 bits/display memory, 512 bytes/melody ram input port .................................... 9 bits (1 bit can be set for event counter external clock input) output port ................................. 7 bits (can be set for bz, bz, tout, tout and fout output) i/o port ....................................... 16 bits (p10?13 and p14?17 can be set for serial i/f input/output and a/d converter input, respectively) serial interface ........................... 1ch (optional clock synchronous system or asynchronous system) timer .......................................... programmable timer (8 bits): 2ch (1ch can be set as a an event counter or 2ch as a 16 bits programmable timer for 1ch) clock timer (8 bits): 1ch stopwatch timer (8 bits): 1ch power supply circuit to drive liquid crystals .. built-in (booster type, 5 potentials/4 potentials) lcd driver .................................. dot matrix type (compatible with 5 8 or 5 5 fonts) 72 segments 32 common (1/5 bias) 88 segments 16 common (1/5 bias or 1/4 bias) 88 segments 8 common (1/5 bias or 1/4 bias) sound generator ........................ envelope function, equipped with volume control watchdog timer .......................... built-in supply voltage detection (svd) circuit .. can detect up to 16 different voltage levels melody generator ....................... 1 sound source (scale: 3 octaves, note: 8 types, tempo: 16 types) note and scale data are stored into the melody ram (allows the cpu to read and write) a/d converter ............................. successive-approximation type, resolution: 10 bits, input: 4ch (shared with p14?17) original architecture core cpu large capacity rom (116k bytes) low current consumption wide-range operating voltage (1.8v to 5.5v) built-in melody generator and a/d converter low voltage operation products
2 S1C88816 interrupt ...................................... external interrupt: input interrupt 2 systems (3 types) internal interrupt: timer interrupt 3 systems (9 types) serial interface interrupt 1 system (3 types) melody interrupt 1 system (1 type) a/d converter interrupt 1 system (1 type) supply voltage ........................... normal mode: 2.4 v?.5 v (max. 4.2 mhz) low power mode: 1.8 v?.5 v (max. 80 khz) high speed mode: 3.5 v?.5 v (max. 8.2 mhz) con-sumed current .................... sleep: 0.45? halt (32.768 khz): 1.5? in operation (32.768 khz): 7? in operation (4 mhz): 0.9ma supply form ................................ qfp18-176pin, or chip block diagram core cpu s1c88 interrupt controller input port oscillator osc1, 2 osc3, 4 reset/test reset test watchdog timer k00?07 k10 (evin) i/o port serial interface output port programmable timer /event counter clock timer stopwatch timer power generator v dd v ss v d1 v osc v c1 ? c5 ca?g supply voltage detector ram 8kb melody generator lcd driver rom 116kb p10 (sin) p11 (sout) p12 (sclk) p13 (srdy) r26 (tout * ) r34 (fout) r50 (bz) r27 (tout) r51 (bz * ) a/d converter sound generator mout mout seg0?eg71 com16?om31 (seg87?eg72) com0?om15 p14?17 (ad4?d7) av dd agnd av ss av ref p00?07 ? selectable by mask option
3 S1C88816 89 132 45 88 index 44 1 176 133 S1C88816 pin configuration qfp18-176pin n.c.: no connection pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 pin name n.c. n.c. seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 n.c. n.c. pin no. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 pin name n.c. seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 seg64 seg65 seg66 seg67 seg68 seg69 seg70 seg71 com31/seg72 com30/seg73 com29/seg74 com28/seg75 com27/seg76 com26/seg77 com25/seg78 com24/seg79 com23/seg80 com22/seg81 com21/seg82 com20/seg83 com19/seg84 com18/seg85 com17/seg86 com16/seg87 cg cf ce cd cc cb ca v c5 v c4 n.c. n.c. pin no. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 pin name n.c. n.c. v c3 v c2 v c1 osc3 osc4 v d1 v dd v ss v osc osc1 osc2 test reset k10/evin k07 k06 k05 k04 k03 k02 k01 k00 p17/ad7 p16/ad6 p15/ad5 p14/ad4 p13/srdy p12/sclk p11/sout p10/sin av dd agnd av ss av ref p07 p06 p05 p04 p03 p02 n.c. n.c. pin no. 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 pin name n.c. n.c. p01 p00 mout mout r26/tout r27/tout r34/fout r50/bz r51/bz com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 n.c.
4 S1C88816 pin description v dd v ss v d1 v osc v c1 ? c5 ca?g osc1 osc2 osc3 osc4 k00?07 k10/evin r26/tout r27/tout r34/fout r50/bz r51/bz p00?07 p10/sin p11/sout p12/sclk p13/srdy p14/ad4 p15/ad5 p16/ad6 p17/ad7 mout mout com0?om15 com16?om31 /seg87?eg72 seg0?eg71 reset test * 1 av dd av ss agnd av ref o i o i o i i o o o o o i/o i/o i/o i/o i/o i/o i/o i/o i/o o o o o o i i i 97 98 96 99 93?1, 86, 85 84?8 100 101 94 95 112?05 104 139 140 141 142 143 136, 135, 130?25 120 119 118 117 116 115 114 113 137 138 144?59 77?2 160?75, 3?2, 46?1 103 102 121 123 122 124 pin no. pin name in/out function power supply (+) terminal power supply (-) terminal regulated voltage for internal circuit regulated voltage for osc1 oscillation circuit lcd drive voltage output terminals voltage boost/reduce-capacitor connection terminals for lcd osc1 oscillation input terminal (select crystal oscillation/cr oscillation/external clock input by mask option) osc1 oscillation output terminal osc3 oscillation input terminal (select crystal/ceramic/cr oscillation/external clock input by mask option) osc3 oscillation output terminal input terminals (k00?07) input terminal (k10) or event counter external clock input terminal (evin) output terminal (r26) or programmable timer underflow signal inverted output terminal (tout) (selectable by mask option) output terminal (r27) or programmable timer underflow signal output terminal (tout) output terminal (r34) or clock output terminal (fout) output terminal (r50) or buzzer output terminal (bz) output terminal (r51) or buzzer inverted output terminal (bz) (selectable by mask option) i/o terminals (p00?07) i/o terminal (p10) or serial i/f data input terminal (sin) i/o terminal (p11) or serial i/f data output terminal (sout) i/o terminal (p12) or serial i/f clock i/o terminal (sclk) i/o terminal (p13) or serial i/f ready signal output terminal (srdy) i/o terminal (p14) or a/d converter input terminal (ad4) i/o terminal (p15) or a/d converter input terminal (ad5) i/o terminal (p16) or a/d converter input terminal (ad6) i/o terminal (p17) or a/d converter input terminal (ad7) melody output terminal melody inverted output terminal lcd common output terminals lcd common output terminals (when 1/32 duty is selected) or lcd segment output terminal (when 1/16 or 1/8 duty is selected) lcd segment output terminals initial reset input terminal test input terminal analog system power supply (+) terminal analog system power supply (? terminal analog system ground terminal analog system reference voltage input terminal ? 1 test is the terminal used for shipping inspection of the ic. for normal operation be sure it is connected to v dd .
5 S1C88816 option list s5u1c88816p option list ao sc1 system clock 1. internal clock (32.768 khz) 2. user clock bo sc3 system clock 1. internal clock (4.9152 mhz) 2. user clock S1C88816 mask option list 1 osc1 system clock 1. crystal 2. external clock 3. cr 4. crystal (with gate capacity) 2 osc3 system clock 1. crystal 2. ceramic 3. cr 4. external clock 3 multiple key entry reset ?combi nation ......... 1. not use 2. use k00, k01 3. use k00, k01, k02 4. use k00, k01, k02, k03 4 svd reset 1. not use 2. use 5 input port pull up resistor ? k00 ............................ 1. with resistor 2. gate direct ? k01 ............................ 1. with resistor 2. gate direct ? k02 ............................ 1. with resistor 2. gate direct ? k03 ............................ 1. with resistor 2. gate direct ? k04 ............................ 1. with resistor 2. gate direct ? k05 ............................ 1. with resistor 2. gate direct ? k06 ............................ 1. with resistor 2. gate direct ? k07 ............................ 1. with resistor 2. gate direct ? k10 ............................ 1. with resistor 2. gate direct ?reset ...................... 1. with resistor 2. gate direct 6 i/o port pull up resistor ? p00 ............................ 1. with resistor 2. gate direct ? p01 ............................ 1. with resistor 2. gate direct ? p02 ............................ 1. with resistor 2. gate direct ? p03 ............................ 1. with resistor 2. gate direct ? p04 ............................ 1. with resistor 2. gate direct ? p05 ............................ 1. with resistor 2. gate direct ? p06 ............................ 1. with resistor 2. gate direct ? p07 ............................ 1. with resistor 2. gate direct
6 S1C88816 ? p10 ............................ 1. with resistor 2. gate direct ? p11 ............................ 1. with resistor 2. gate direct ? p12 ............................ 1. with resistor 2. gate direct ? p13 ............................ 1. with resistor 2. gate direct ? p14 ............................ 1. with resistor 2. gate direct ? p15 ............................ 1. with resistor 2. gate direct ? p16 ............................ 1. with resistor 2. gate direct ? p17 ............................ 1. with resistor 2. gate direct 7 lcd dr ive duty 1. 1/32 & 1/16 duty 2. 1/8 duty 8 lcd power supply 1. internal type a (v c2 standard, 1/5 bias, 4.5 v) 2. external 3. internal type b (v c2 standard, 1/5 bias, 5.5 v) 4. internal type c (v c2 standard, 1/4 bias, 4.5 v) 5. internal type d (v c1 standard, 1/4 bias, 4.5 v) 9 bz output (r51) 1. use 2. not use 10 tout output (r26) 1. use 2. not use 11 cpu mode 1. maximum mode 2. minimum mode 12 mode during buzzer output 1. normal mode 2. heavy load protection mode 13 mode during melody output 1. normal mode 2. heavy load protection mode electrical characteristics absolute maximum ratings item symbol unit rated value power voltage liquid crystal power voltage input voltage output voltage high level output current low level output current permitted loss operating temperature storage temperature soldering temperature / time v dd v c5 v i v o i oh i ol p d topr tstg tsol v v v v ma ma ma ma mw c c -0.3 to +7.0 -0.3 to +7.0 -0.3 to v dd + 0.3 -0.3 to v dd + 0.3 -5 -20 5 20 200 -40 to +85 -65 to +150 260 c, 10sec ( lead section ) note) note 1 2 condition 1 terminal total of all terminals 1 terminal total of all terminals 1 2 case that to nch open drain output by the mask option is included. in case of plastic packa g e. (v ss =0v)
7 S1C88816 recommended operating conditions item symbol min. typ. max. unit condition operating power voltage (normal mode) operating power voltage (low power mode) operating power voltage (high speed mode) analog power voltage operating frequency (normal mode) operating frequency (low power mode) operating frequency (high speed mode) liquid crystal power voltage capacitor between v d1 and v ss capacitor between v c1 and v ss capacitor between v c2 and v ss capacitor between v c3 and v ss capacitor between v c4 and v ss capacitor between v c5 and v ss capacitor between ca and cb capacitor between ca and cc capacitor between cd and ce capacitor between cf and cg v dd v dd v dd av dd f osc1 f osc3 f osc1 f osc1 f osc3 v c5 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 2.4 1.8 3.5 v dd -0.05 30.000 0.03 30.000 30.000 0.03 32.768 32.768 32.768 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 5.5 5.5 5.5 v dd +0.05 80.000 4.2 80.000 80.000 8.2 6.0 v v v v khz mhz khz khz mhz v f f f f f f f f f f av dd 2.7 v v dd = 2.4 to 5.5 v v dd = 1.8 to 5.5 v v dd = 3.5 to 5.5 v v c5 v c4 v c3 v c2 v c1 v ss note 1 1 1 1 1 2 3 3 3 3 3 3 3 3 3 (v ss =0v, ta=-40 to 85 c) note) 1 2 3 when an external clock is input from the osc1 terminal by the mask option, leave the osc2 terminal open, and when an external clock is input from the osc3 terminal, leave the osc4 terminal open. when external power supply is selected by the mask option. when lcd drive power is not used, the capacitor is not necessar y . in this case, leave the v c1 to v c5 and ca to cg terminals open. dc characteristics item symbol min. typ. max. unit condition high level input voltage (1) low level input voltage (1) high level input voltage (2) (normal mode) high level input voltage (2) high level input voltage (2) (high speed mode) low level input voltage (2) (normal mode) low level input voltage (2) low level input voltage (2) (high speed mode) high level schmitt input voltage low level schmitt input voltage high level output current low level output current input leak current output leak current input pull-up resistance input terminal capacitance segment/common output current v ih1 v il1 v ih2 v ih2 v ih2 v il2 v il2 v il2 v t+ v t- i oh i ol i li i lo r in c in i segh i segl 0.8v dd 0 1.6 1.0 2.4 0 0 0 0.5v dd 0.1v dd 0.5 -1 -1 100 5 300 7 v dd 0.2v dd v dd v dd v dd 0.6 0.3 0.9 0.9v dd 0.5v dd -0.5 1 1 500 15 -5 v v v v v v v v v v ma ma a a k ? pf a a kxx, pxx kxx, pxx osc3 osc1 osc3 osc3 osc1 osc3 reset reset pxx, rxx, v oh = 0.9v dd pxx, rxx, v ol = 0.1v dd kxx, pxx, reset pxx, rxx kxx, pxx, reset kxx, pxx, v in = 0v, f = 1mhz, ta = 25 c segxx, comxx, v segh = v c5 -0.1v segxx, comxx, v segl = 0.1v note 1 1 1 1 1 1 2 (unless otherwise specified: v dd =1.8 to 5.5v, v ss =0v, ta=-40 to 85 c ) note) 1 2 when external clock is selected by mask option. when pull-up resistor is added b y mask option. v dd 0 v dd v t+ v in [v] v out [v] v t- 0
8 S1C88816 lcd driver the typ. values of the lcd drive voltage shown in the following table shift in difference of panel load (panel size, drive duty , display segment number). therefore, these should be evaluated by connecting to the actual panel to be used. item symbol min. typ. max. unit condition lcd drive voltage (v c2 standard) lcd drive voltage (v c1 standard) v c2 v c5 type a (4.5v) v c5 type b (5.5v) v c5 type c (5.5v) v c1 v c5 type d (4.5v) 0.412v c5 3.52 3.64 3.76 3.88 4.00 4.12 4.24 4.37 4.51 4.63 4.75 4.87 5.00 5.12 5.24 5.36 4.20 4.34 4.49 4.63 4.78 4.92 5.07 5.21 5.36 5.50 5.65 5.80 5.94 6.09 6.23 6.38 3.34 3.54 3.66 3.78 3.90 4.02 4.14 4.26 4.38 4.49 4.61 4.73 4.85 4.97 5.09 5.21 0.260v c5 3.80 3.88 3.96 4.03 4.15 4.22 4.30 4.38 4.45 4.53 4.65 4.72 4.80 4.88 4.95 5.07 v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v note (unless otherwise specified: v dd =v c2 (lcx=fh) + 0.1 to 5.5v, v ss =0v, ta=25 c, c 1 ? 10 =0.1 f) lcx = 0h lcx = 1h lcx = 2h lcx = 3h lcx = 4h lcx = 5h lcx = 6h lcx = 7h lcx = 8h lcx = 9h lcx = ah lcx = bh lcx = ch lcx = dh lcx = eh lcx = fh lcx = 0h lcx = 1h lcx = 2h lcx = 3h lcx = 4h lcx = 5h lcx = 6h lcx = 7h lcx = 8h lcx = 9h lcx = ah lcx = bh lcx = ch lcx = dh lcx = eh lcx = fh lcx = 0h lcx = 1h lcx = 2h lcx = 3h lcx = 4h lcx = 5h lcx = 6h lcx = 7h lcx = 8h lcx = 9h lcx = ah lcx = bh lcx = ch lcx = dh lcx = eh lcx = fh lcx = 0h lcx = 1h lcx = 2h lcx = 3h lcx = 4h lcx = 5h lcx = 6h lcx = 7h lcx = 8h lcx = 9h lcx = ah lcx = bh lcx = ch lcx = dh lcx = eh lcx = fh note ) 1 fixin g the lcd contrast is not recommended. a contrast ad j ustment function should be included in the software. typ 0.94 typ 0.94 typ 0.94 typ 0.94 typ 1.06 typ 1.06 typ 1.06 typ 1.06 when 1 m ? load resistor is connected between v ss and v c2 (no panel load) when 1 m ? load resistor is connected between v ss and v c5 (no panel load) when 1 m ? load resistor is connected between v ss and v c5 (no panel load) when 1 m ? load resistor is connected between v ss and v c5 (no panel load) when 1 m ? load resistor is connected between v ss and v c1 (no panel load) when 1 m ? load resistor is connected between v ss and v c5 (no panel load) 1 1 1 1
9 S1C88816 svd circuit item symbol min. typ. max. unit condition svd voltage v svd typ 0.92 typ 0.88 1.82 2.00 2.18 2.36 2.54 2.72 2.90 3.08 3.26 3.45 3.65 3.85 4.00 4.15 4.35 typ 1.08 typ 1.12 v v v v v v v v v v v v v v v level 1 level 0 level 2 level 1 level 3 level 2 level 4 level 3 level 5 level 4 level 6 level 5 level 7 level 6 level 8 level 7 level 9 level 8 level 10 level 9 level 11 level 10 level 12 level 11 level 13 level 12 level 14 level 13 level 15 level 14 note 1 1 1 2 2 2 3 3 3 4 4 4 4 4 4 (unless otherwise specified: v dd =1.8 to 5.5v, v ss =0v, ta=25 c) note) 1 2 3 4 low power operating mode only low power operating mode or normal operating mode only normal operating mode only normal operatin g mode or hi g h speed operatin g mode onl y v svd (level 0) < v svd (level 1) < v svd (level 2) < v svd (level 3) < v svd (level 4) < v svd (level 5) < v svd (level 6) < v svd (level 7) < v svd (level 8) < v svd (level 9) < v svd (level 10) < v svd (level 11) < v svd (level 12) < v svd (level 13) < v svd (level 14) < v svd (level 15) current consumption item symbol min. typ. max. unit condition power current (normal mode) power current (low power mode) power current (high speed mode) lcd drive circuit current svd circuit current osc1 cr oscillation current (r cr1 = 500 k ? ) i dd1 i dd2 i dd3 i dd4 i dd1 i dd2 i dd3 i dd1 i dd2 i dd3 i dd4 i lcdn i lcdh i svdn i cr1 a a a ma a a a a a a ma a a a a in sleep status in halt status cpu is in operating (32.768 khz) cpu is in operating (4 mhz) in sleep status in halt status cpu is in operating (32.768 khz) in sleep status in halt status cpu is in operating (32.768 khz) cpu is in operating (8 mhz) in heavy load protection mode v dd = 3.0 v in halt status (50 khz) note 1 2 3 4 ? 1 ? 2 ? 3 ? 4 ? 5 osc1: stop, osc3 = stop, cpu, rom, ram: sleep status, clock timer: stop, others: stop status osc1: oscillating, osc3 = stop, cpu, rom, ram: halt status, clock timer: operating, others: stop status osc1: oscillating, osc3 = stop, cpu, rom, ram: operating in 32.768 khz, clock timer: operating, others: stop status osc1: oscillating, osc3 = oscillating, cpu, rom, ram: operating in 4 mhz, clock timer: operating, others: stop status osc1: oscillating, osc3 = oscillating, cpu, rom, ram: operating in 8 mhz, clock timer: operating, others: stop status the lcd drive circuit current varies according to the display patterns. heavy load protection circuit current in heavy load protection mode when the osc3 oscillation circuit is turned on, the ic always enters heavy load protection mode. the mode while the buzzer or melody signals are being output can be selected by mask option. when using a bipolar transistor as the example of the r50 terminal shown in " basic external connection diagram", select heavy load protection mode. when direct driving a piezoelectric buzzer as the example of the mout and /mout terminals, select normal mode. the value in x v can be found by the following expression: i svdn (v dd = x v) = ( x 20) - 30 (typ. value), i svdn (v dd = x v) = ( x 30) - 30 (max. value) when osc1 cr oscillation circuit is selected by the mask option. ? 1 ? 2 ? 3 ? 4 ? 1 ? 2 ? 3 ? 1 ? 2 ? 3 ? 5 note) 1 2 3 4 (unless otherwise specified: v dd =within the operating voltage in each operating mode, v ss =0v, ta=25 c, osc1=32.768khz crystal oscillation, c g =25pf, osc3=crystal/ceramic oscillation, non heavy load protection mode, c 1 ? 10 =0.1 f, no panel load) 0.45 1.5 7 0.9 0.30 1 5 1 2 12 3.3 6 37 27 10 1.6 3.5 10 1.1 1 2.5 7 3 5 16 3.9 10 45 40 15
10 S1C88816 ac characteristics external memory access item item min. typ. max. unit condition operating frequency (normal mode) operating frequency ( low power mode ) operating frequency (high speed mode) instruction execution time (during operation with osc1 clock) instruction execution time normal mode ( during operation with osc3 clock ) instruction execution time high speed mode (during operation with osc3 clock) f osc1 f osc3 f osc1 f osc1 f osc3 t cy t cy t cy 30.000 0.03 30.000 30.000 0.03 25 50 75 100 125 150 0.5 1.0 1.4 1.9 2.4 2.9 0.2 0.5 0.7 1.0 1.2 1.5 32.768 32.768 32.768 61 122 183 244 305 366 80.000 4.2 80.000 80.000 8.2 67 133 200 267 333 400 66.7 133.3 200.0 266.7 333.3 400.0 66.7 133.3 200.0 266.7 333.3 400.0 khz mhz khz khz mhz s s s s s s s s s s s s s s s s s s v dd = 2.4 to 5.5 v v dd = 1.8 to 5.5 v v dd = 3.5 to 5.5 v 1-cycle instruction 2-cycle instruction 3-cycle instruction 4-cycle instruction 5-cycle instruction 6-cycle instruction 1-cycle instruction 2-cycle instruction 3-cycle instruction 4-cycle instruction 5-cycle instruction 6-cycle instruction 1-cycle instruction 2-cycle instruction 3-cycle instruction 4-cycle instruction 5-cycle instruction 6-cycle instruction note (condition: v dd =within the operating voltage in each operating mode, v ss =0v, ta=-40 to 85 c) serial interface ?clock synchronous master mode (normal operating mode) item transmitting data output delay time receiving data input set-up time receiving data input hold time symbol t smd t sms t smh unit ns ns ns note max. 200 typ. min. 500 200 (condition: v dd =2.4 to 5.5v, v ss =0v, ta=-40 to 85 c, v ih1 =0.8v dd , v il1 =0.2v dd , v oh =0.8v dd , v ol =0.2v dd ) ?clock synchronous master mode (high speed operating mode) item transmitting data output delay time receiving data input set-up time receiving data input hold time symbol t smd t sms t smh unit ns ns ns note max. 100 typ. min. 250 200 (condition: v dd =3.5 to 5.5v, v ss =0 v, ta=-40 to 85 c, v ih1 =0.8v dd , v il1 =0.2v dd , v oh =0.8v dd , v ol =0.2v dd ) ?clock synchronous master mode (low power operating mode) item transmitting data output delay time receiving data input set-up time receiving data input hold time symbol t smd t sms t smh unit s s s note max. 5 typ. min. 10 5 (condition: v dd =1.8 to 5.5v, v ss =0v, ta=-40 to 85 c, v ih1 =0.8v dd , v il1 =0.2v dd , v oh =0.8v dd , v ol =0.2v dd ) ?clock synchronous slave mode (normal operating mode) item transmitting data output delay time receiving data input set-up time receiving data input hold time symbol t ssd t sss t ssh unit ns ns ns note max. 500 typ. min. 200 200 (condition: v dd =2.4 to 5.5v, v ss =0v, ta=-40 to 85 c, v ih1 =0.8v dd , v il1 =0.2v dd , v oh =0.8v dd , v ol =0.2v dd )
11 S1C88816 ?clock synchronous slave mode (high speed operating mode) item transmitting data output delay time receiving data input set-up time receiving data input hold time symbol t ssd t sss t ssh unit ns ns ns note max. 250 typ. min. 100 100 (condition: v dd =3.5 to 5.5v, v ss =0v, ta=-40 to 85 c, v ih1 =0.8v dd , v il1 =0.2v dd , v oh =0.8v dd , v ol =0.2v dd ) ?clock synchronous slave mode (low power operating mode) item transmitting data output delay time receiving data input set-up time receiving data input hold time symbol t ssd t sss t ssh unit s s s note max. 10 typ. min. 5 5 (condition: v dd =1.8 to 5.5v, v ss =0 v, ta=-40 to 85 c, v ih1 =0.8v dd , v il1 =0.2v dd , v oh =0.8v dd , v ol =0.2v dd ) ?asynchronous system (all operating mode) item start bit detection error time erroneous start bit detection range time note) 1 2 symbol t sa 1 t sa 2 unit s s note 1 2 max. t /16 10 t /16 typ. min. 0 9 t /16 start bit detection error time is a logical delay time from inputting the start bit until internal sampling begins operating. (time as far as ac is excluded.) erroneous start bit detection range time is a logical range to detect whether a low level (start bit) has been input again after a start bit has been detected and the internal sampling clock has started. when a high level is detected, the start bit detection circuit is reset and goes into a wait status until the next start bit. (time as far as ac is excluded.) (condition: v dd =1.8 to 5.5v, v ss =0v, ta=-40 to 85 c) sclk out sout sin v oh v oh v ol t sms t smh t smd v ih1 v il1 v ol sclk in sout sin v ih1 v oh v ol t sss t ssh t ssd v ih1 v il1 v il1 t sa 1 t t sa 2 sin start bit sampling clock erroneous start bit detection signal stop bit
12 S1C88816 input clock ?osc1, osc3 external clock (normal operating mode) symbol t o 1 cy t o 1 h t o 1 l t o 3 cy t o 3 h t o 3 l t osr t osf unit s s s ns ns ns ns ns note max. 32 16 16 32,000 16,000 16,000 25 25 typ. min. 12 6 6 250 125 125 (condition: v dd =2.4 to 5.5v, v ss =0v, ta=-40 to 85 c, v ih2 =1.6 v, v il2 =0.6v) item osc1 input clock time cycle time "h" pulse width "l" pulse width osc3 input clock time cycle time "h" pulse width "l" pulse width input clock rising time input clock falling time ?osc1, osc3 external clock (high speed operating mode) symbol t o 1 cy t o 1 h t o 1 l t o 3 cy t o 3 h t o 3 l t osr t osf unit s s s ns ns ns ns ns note max. 32 16 16 32,000 16,000 16,000 25 25 typ. min. 12 6 6 125 62.5 62.5 (condition: v dd =3.5 to 5.5v, v ss =0v, ta=-40 to 85 c, v ih2 =1.6v, v il2 =0.6v) item osc1 input clock cycle time "h" pulse width "l" pulse width osc3 input clock time cycle time "h" pulse width "l" pulse width input clock rising time input clock falling time ?osc1 external clock (low power operating mode) symbol t o 1 cy t o 1 h t o 1 l t osr t osf unit s s s ns ns note max. 32 16 16 25 25 typ. min. 12 6 6 (condition: v dd =1.8 to 5.5v, v ss =0v, ta=-40 to 85 c, v ih2 =1.0v, v il2 =0.3v) item osc1 input clock time cycle time "h" pulse width "l" pulse width input clock rising time input clock falling time osc1 osc3 v ih2 t o 1 cy t o 1 h v il2 t osf t osr t o 1 l v ih2 t o 3 cy t o 3 h v il2 t osf t osr t o 3 l ?sclk, evin input clock (normal operating mode) system t sccy t sch t scl t evcy t evh t evl t evcy t evh t evl t ckr t ckf unit s s s s s s s s s ns ns note max. 25 25 typ. min. 4 2 2 64/f osc1 32/f osc1 32/f osc1 4 2 2 (condition: v dd =2.4 to 5.5v, v ss =0v, ta=-40 to 85 c, v ih1 =0.8v dd , v il1 =0.2v dd ) item sclk input clock time cycle time "h" pulse width "l" pulse width evin input clock time cycle time (with noise rejector) "h" pulse width "l" pulse width evin input clock time cycle time (without noise rejector) "h" pulse width "l" pulse width input clock rising time input clock falling time
13 S1C88816 ?sclk, evin input clock (high speed operating mode) system t sccy t sch t scl t evcy t evh t evl t evcy t evh t evl t ckr t ckf unit s s s s s s s s s ns ns note max. 25 25 typ. min. 2 1 1 64/f osc1 32/f osc1 32/f osc1 2 1 1 (condition: v dd =3.5 to 5.5v, v ss =0v, ta=-40 to 85 c, v ih1 =0.8v dd , v il1 =0.2v dd ) item sclk input clock time cycle time "h" pulse width "l" pulse width evin input clock time cycle time (with noise rejector) "h" pulse width "l" pulse width evin input clock time cycle time (without noise rejector) "h" pulse width "l" pulse width input clock rising time input clock falling time ?sclk, evin input clock (low power operating mode) symbol t sccy t sch t scl t evcy t evh t evl t evcy t evh t evl t ckr t ckf unit s s s s s s s s s ns ns note max. 25 25 typ. min. 100 50 50 64/f osc1 32/f osc1 32/f osc1 100 50 50 (condition: v dd =1.8 to 5.5v, v ss =0v, ta=-40 to 85 c, v ih1 =0.8v dd , v il1 =0.2v dd ) item sclk input clock time cycle time "h" pulse width "l" pulse width evin input clock time cycle time (with noise rejector) "h" pulse width "l" pulse width evin input clock time cycle time (without noise rejector) "h" pulse width "l" pulse width input clock rising time input clock falling time sclk evin v ih1 t sccy t sch v il1 t ckf t ckr t scl v ih1 t evcy t evh v il1 t ckf t ckr t evl ?reset input clock (all operating mode) item reset input time symbol t sr unit s note max. typ. min. 100 (condition: v dd =1.8 to 5.5v, v ss =0v, ta=-40 to 85 c, v ih =0.5v dd, v il =0.1v dd ) reset t sr v il v ih
14 S1C88816 power on reset item operating power voltage reset input time symbol vsr t psr unit v ms note max. typ. min. 2.4 10 (condition: v ss =0v, ta=-40 to 85 c) v dd reset t psr vsr 0.5v dd 0.1v dd power on ? 1 when the built-in pull up resistor is not used. ? 2 because the potential of the reset terminal not reached v dd level or higher. v dd reset v ss ? 2 ? 1 operating mode switching item stabilization time note) 1 symbol t vdc unit ms note 1 max. typ. min. 5 stabilization time is the time from switching on the operating mode until operating mode is stabilized. for example, when turni ng the osc3 oscillation circuit on, stabilization time is needed after the operating mode is switched on. (condition: v dd =1.8 to 5.5v, v ss =0v, ta=-40 to 85 c) oscillation characteristics oscillation characteristics change depending on conditions (board pattern, components used, etc.). use the following char- acteristics as reference values. in particular, when a ceramic oscillator is used for osc3, use the oscillator manufacturer? recommended values for constants such as capacitance and resistance. the oscillation start time is important because it becomes the wait time when osc3 clock is used. (if osc3 is used as cpu clock before oscillation stabilizes, the cpu may malfunction.) osc1 (crystal) item symbol min. typ. max. unit condition oscillation start time external gate capacitance built-in gate capacitance built-in drain capacitance frequency/ic deviation frequency/power voltage deviation frequency adjustment range frequency/operating mode deviation t sta c g1 c g1 c d1 ? f / ? ic ? f / ? v ? f / ? c g ? f / ? md 5 -10 25 12 12 55 3 30 10 1 20 s pf pf pf ppm ppm/v ppm ppm including board capacitance in case of the chip in case of the chip v dd = constant v dd = constant, c g = 5 to 30 pf v dd = constant note 1 2 1 note) ? 1 2 q12c2 made by seiko epson corporation when crystal oscillation (external gate capacitor type) is selected by mask option. when cr y stal oscillation ( g ate capacitor built-in t y pe) is selected b y mask option. (unless otherwise specified: v dd =within the operating voltage in each operating mode, v ss =0v, ta=25 c, crystal oscillator=q12c2 * , c g1 =25pf (external), c d1 =built-in)
15 S1C88816 osc1 (cr) item symbol min. typ. max. unit condition oscillation start time frequency/ic deviation t sta ? f / ? ic -25 3 25 ms % r cr = constant note (unless otherwise specified: v dd =2.4 to 5.5v, v ss =0v, ta=-40 to 85 c) osc3 (crystal) item symbol min. typ. max. unit condition oscillation start time (normal mode) oscillation start time (high speed mode) t sta t sta 20 20 ms ms 4.0 mhz crystal oscillator 8.0 mhz crystal oscillator note 1 1 note) ? 1 q21ca301xxx made by seiko epson corporation the crystal oscillation start time changes by the crystal oscillator to be used, c g2 and c d2 . (unless otherwise specified: v dd =within the operating voltage in each operating mode, v ss =0v, ta=25 c, crystal oscillator=q21ca301xxx * , r f =1m ? , c g2 =c d2 =15pf) osc3 (ceramic) item symbol min. typ. max. unit condition oscillation start time (normal mode) oscillation start time (high speed mode) 5 5 ms ms 4.0 mhz ceramic oscillator 8.0 mhz ceramic oscillator note ? csa4.00mg / csa8.00mtz made by murata mfg. corporation (unless otherwise specified: v dd =within the operating voltage in each operating mode, v ss =0v, ta=25 c, ceramic oscillator=csa4.00mg / csa8.00mtz * , r f =1m ? , c g2 =c d2 =30pf) t sta t sta osc3 (cr) item symbol min. typ. max. unit condition oscillation start time (normal mode) oscillation start time (high speed mode) frequency/ic deviation (normal mode) frequency/ic deviation (high speed mode) t sta t sta ? f / ? ic ? f / ? ic -25 -25 1 1 25 25 ms ms % % r cr = constant r cr = constant note (unless otherwise specified: v dd =within the operating voltage in each operating mode, v ss =0v, ta=-40 to 85 c) a/d converter characteristics item symbol min. typ. max. unit condition zero-scale error full-scale error non-linearity error total error a/d converter current consumption input clock frequency ezs efs el et i ad f -1.50 -1.50 -1.50 -3.00 0.50 1.80 1.50 1.50 1.50 3.00 1.00 3.50 2 4 lsb lsb lsb lsb ma ma mhz mhz v dd =av dd =av ref =2.7 to 5.5v, adclk=2mhz, ta=25 c v dd =av dd =av ref =3.0v, adclk=2mhz, ta=25 c av ref and adclk divider current not included v dd =av dd =av ref =5.0v, adclk=2mhz, ta=25 c av ref and adclk divider current not included v dd =av dd =av ref =2.7 to 3.0 v, ta=25 c v dd =av dd =av ref =3.0 to 5.5 v, ta=25 c note ? ? ? ? zero-scale error: ezs = deviation from the ideal value at zero point full-scale error: efs = deviation from the ideal value at the full scale point non-linearity error: el = deviation of the real conversion curve from the end point line total error: et = max(ezs, efs, eabs), eabs = deviation from the ideal line (including quantization error) the following characteristics apply to the plastic package model only. (unless otherwise specified: v dd =av dd =av ref =5.0v, v ss =av ss =agnd=0v, f osc1 =32.768khz, f osc3 =4.0mhz, ta=25 c)
16 S1C88816 basic external connection diagram when v c2 standard and 1/5 bias are selected recommended values for external parts [the potential of the substrate (back of the chip) is v ss .] n.c. S1C88816 lcd panel 72 x 32 v ss av ss agnd v osc osc1 osc2 osc3 osc4 v d1 v c1 v c2 v c3 v c4 v c5 ca cb cc cd ce cf cg reset v dd av dd av ref test k00 k01 k02 k03 k04 k05 k06 k07 k10 r26 (tout) r27 (tout) r34 (fout) r51 (bz) p00 p01 p02 p03 p04 p05 p06 p07 p10 (sin) p11 (sout) p12 (sclk) p13 (srdy) p14 (ad4) p15 (ad5) p16 (ad6) p17 (ad7) c g2 c g1 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 x'tal1 rf cres 3 v c p1 r50 (bz) + c p2 + c p3 + piezo coil seg0 seg71 com0 com31 x'tal2 or ceramic r cr3 r cr1 c d2 ? 2 ? 5 ? 1 ? 3 ? 4 rm rm mout mout piezo x'tal1 c g1 r cr1 x'tal2 ceramic rf c g2 c d2 r cr3 crystal oscillator trimmer capacitor resistor for cr oscillation crystal oscillator ceramic oscillator feedback resistor gate capacitor drain capacitor resistor for cr oscillation 32.768 khz, ci(max.)=35 k ? 5?0 pf 1 m ? 4 mhz 4 mhz 1 m ? 15 pf (crystal oscillator) 30 pf (ceramic oscillator) 15 pf (crystal oscillator) 30 pf (ceramic oscillator) 20 k ? c 1 c 2 c 3 c 4 c 5 c 6 c 7 ? 10 c p1 c p3 cres rm capacitor between v ss and v d1 capacitor between v ss and v c1 capacitor between v ss and v c2 capacitor between v ss and v c3 capacitor between v ss and v c4 capacitor between v ss and v c5 booster/reducer capacitors capacitors for power supply capacitor for reset terminal protective resistors for piezo 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 3.3 f 0.47 f 100 ? symbol name recommended value symbol name recommended value ? the connection diagram shown above is an example of when mask option settings are as follows: lcd power source: internal power supply, reset terminal: with pull-up resistor, r51 specification: general-purpose output port ? 1 osc1 = crystal oscillation, ? 2 osc1 = cr oscillation, ? 3 osc3 = crystal/ceramic oscillation, ? 4 osc3 = cr oscillation, ? 5 unnecessary for 1/4 bias drive note: the above table is simply an example, and is not guaranteed to work.
17 S1C88816 diagram of pad layout 160 y x (0, 0) 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 155 5.38 mm 5.40 mm die no. chip thickness: 0.4 mm pad opening: 95 ? pad coordinates pad no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 pad name v c3 v c2 v c1 osc3 osc4 v d1 v dd v ss v osc osc1 osc2 test reset k10/evin k07 k06 k05 k04 k03 k02 k01 k00 p17/ad7 p16/ad6 p15/ad5 p14/ad4 x 2,319 2,204 2,089 1,974 1,859 1,744 1,629 1,514 1,399 1,284 1,169 1,054 939 824 709 594 479 364 249 134 19 -96 -211 -326 -441 -556 y 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 pad no. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 pad name p13/srdy p12/sclk p11/sout p10/sin av dd agnd av ss av ref p07 p06 p05 p04 p03 p02 p01 p00 mout mout r26/tout r27/tout r34/fout r50/bz r51/bz com0 com1 com2 x -671 -786 -901 -1,016 -1,131 -1,246 -1,361 -1,476 -1,591 -1,706 -1,821 -1,936 -2,051 -2,166 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 y 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 2,569 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 pad no. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 pad name com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 x -2,558 -2,558 -2,558 2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 -2,558 y -2,558 -2,558 -2,558 622 507 392 277 162 47 -68 -183 -298 -413 -528 -643 -758 -873 -988 -1,103 -1,218 -1,333 -1,448 -1,563 -1,678 -1,793 -1,908
18 S1C88816 pad no. 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 pad name seg13 seg14 seg15 ? seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 x -2,558 -2,558 -2,558 ? -2,243 -2,128 -2,013 -1,898 -1,783 -1,668 -1,553 -1,438 -1,323 -1,208 -1,093 -978 -863 -748 -633 -518 -403 -288 -173 -58 58 173 288 403 518 y -2,023 -2,137 -2,252 ? -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 pad no. 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 pad name seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 ? seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 seg64 seg65 seg66 seg67 seg68 x 633 748 863 978 1,093 1,208 1,323 1,438 1,553 1,668 1,783 1,898 2,013 2,128 2,243 ? 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 y -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 -2,569 ? 2,253 -2,138 -2,023 -1,908 -1,793 -1,678 -1,563 -1,448 -1,333 -1,218 -1,103 -988 -873 pad no. 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 pad name seg69 seg70 seg71 com31/seg72 com30/seg73 com29/seg74 com28/seg75 com27/seg76 com26/seg77 com25/seg78 com24/seg79 com23/seg80 com22/seg81 com21/seg82 com20/seg83 com19/seg84 com18/seg85 com17/seg86 com16/seg87 cg cf ce cd cc cb ca v c5 v c4 x 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 2,558 y -758 -643 -528 -413 -298 -183 -68 47 162 277 392 507 622 737 852 967 1,082 1,197 1,312 1,427 1,542 1,657 1,772 1,887 2,002 2,117 2,232 2,347 ? do not bond no.82 and 123 pads since they are used for factory inspection at shipment. package dimensions plastic qfp18-176pin 24 0.1 26 0.4 89 132 24 0.1 26 0.4 45 88 index 0.2 44 1 176 133 2.7 0.1 0.1 3 max 0.5 0.2 0 10 0.15 0.05 0.5 +0.1 ?.05 1 unit: mm
19 S1C88816 ceramic pga-181pin 39.5 0.3 39.5 0.3 2.54 1.3 index 1.3 0.2 0.46 0.04 15 90 89 88 87 86 85 84 83 54 53 52 51 50 49 45 91 82 81 80 79 78 77 76 59 58 57 56 55 38 44 92 98 75 74 73 72 71 70 63 62 61 60 32 37 43 93 99 104 69 67 66 65 64 48 47 46 27 31 36 42 94 100 105 109 68 26 30 35 41 95 101 106 110 25 29 34 40 96 102 107 111 24 28 33 39 97 103 108 112 113 23 22 18 13 7 129 123 118 114 21 17 12 6 130 124 119 115 20 16 11 5 131 125 120 116 158 19 15 10 4 132 126 121 117 136 137 138 154 155 156 157 159 14 9 3 133 127 122 150 151 152 153 160 161 162 163 164 165 8 2 134 128 145 146 147 148 149 166 167 168 169 170 171 172 1 14 13 12 11 10 987654 q p n m l k j h g f e d 32 c b 1 a 135 139 140 141 142 143 144 173 174 175 176 177 178 179 180 top view bottom view miss insertion protect pin unit: mm pin no. pin name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 pin no. pin name seg49 seg50 seg51 seg52 seg53 seg54 seg55 n.c. n.c. n.c. n.c. seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 seg64 seg65 seg66 seg67 seg68 seg69 seg70 seg71 com31/seg72 com30/seg73 com29/seg74 com28/seg75 com27/seg76 com26/seg77 com25/seg78 com24/seg79 com23/seg80 n.c. n.c. n.c. seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 pin no. pin name 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 com22/seg81 com21/seg82 com20/seg83 com19/seg84 com18/seg85 com17/seg86 com16/seg87 cg cf ce cd cc cb ca v c5 v c4 n.c. n.c. n.c. n.c. n.c. v c3 v c2 v c1 osc3 osc4 v d1 v dd v ss v osc osc1 osc2 test reset k10/evin k07 n.c.: no connection pin no. pin name pin no. pin name 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 k06 k05 k04 k03 k02 k01 k00 p17/ad7 p16/ad6 p15/ad5 p14/ad4 p13/srdy p12/sclk p11/sout p10/sin av dd agnd av ss av ref p07 p06 p05 p04 p03 p02 n.c. n.c. n.c. n.c. p01 p00 mout mout r26/tout r27/tout r34/fout 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 r50/bz r51/bz com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 n.c. n.c. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
S1C88816 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 2001 all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department europe & u.s.a. 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department asia 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110 http://www.epson.co.jp/device/ epson electronic devices website first issue september, 2000 m printed august, 2001 in japan l

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